1. Field of the Invention
The present invention relates to an image processing system and method thereof, especially to an image processing system with a 4-T (4 transistors) pixel capable of reducing fixed pattern noise and method thereof.
2. Description of the Prior Art
Recently, CMOS image sensors (CIS) instead of CCDs (Charge-coupled devices) have become the main stream of image sensors utilized in image processing systems. The CMOS image sensors have advantages of low cost and low power consumption, and they are capable of being designed with SOC (system-on-chip) technique when compared with CCDs. As the image processing technology evolves, a 3-T (3 transistors) pixel applied in the image processing systems is gradually replaced by a 4-T (4 transistors) pixel due to better performance and efficiency.
However, the CMOS image sensors have fixed pattern noises (FPN) caused by the differences between the parameters of the device. Please refer to FIG. 1. FIG. 1 is an image with FPN equal to 2.41%. Generally, an image sensor can be divided into 2 portions, the photo detector array and the readout circuitry. The FPN in the CIS system may be induced by pixels and by the readout circuitry. The FPN induced by pixels is normally due to the mismatches of the pixel dark current and the source follower in the pixel array, and the FPN induced by the readout circuitry is due to the readout architecture and certain offsets. The most serious FPN in the CIS system is the FPN induced by the readout circuitry. Generally speaking, the FPN in the readout circuitry can be divided into 5 categories:
(1) FPN—1: pixel FPN (too small to be considered).
(2) FPN—2: random offsets between even/odd neighboring columns.
(3) FPN—3: offsets between even and odd columns.
(2) FPN—4: gradually decreased outputs in even/odd columns.
(5) FPN—5: offsets between top and bottom readout rows.
Please refer to FIG. 2. FIG. 2 is an image illustrating the 5 categories of FPN in the readout circuitry. In FIG. 2, “e” denotes an even column; “o” denotes an odd column; “TOP” denotes a row for top readout; “Bottom” denotes a row for bottom readout. An image of high quality should have overall FPN kept under 1%. The effective technique used to reduce FPN is correlated double sampling (CDS). However, the CDS is very complicated.
Please refer to FIG. 3. FIG. 3 shows a block diagram of the prior art image process system 400. The image process system 400 includes a 4-T pixel 1000, a second portion 1600 of a linearized source follower, a ping pong memory 2000, and a PGA (programmable gain amplifier) 250. The 4-T pixel 1000 includes a first portion of a linearized source follower. The second portion 1600 of the linearized source follower is coupled between the 4-T pixel 1000 and the ping pong memory 2000. The ping pong memory 2000 is coupled between the second portion 1600 of the linearized source follower and the PGA 250. The PGA 250 includes an op amp, and the PGA 250 is a close loop. Thus, an unwanted offset voltage at the output of the op amp will be feed backed to an input of the PGA 250 and thereby generate FPN of more than 1%, which is an unacceptable level.